1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices. More specifically, the invention relates to a semiconductor integrated circuit device including a circuit for generating an internal supply voltage to be provided to a sense amplifier.
2. Description of the Background Art
The operating supply voltage of recent semiconductor integrated circuit devices has remarkably been decreasing. As an example, an array operating potential Vdds is now considered that is an operating supply potential of a sense amplifier and is equal to H data written into a memory cell of a dynamic random access memory (DRAM).
In general, array operating potential Vdds is generated by internally decreasing an external supply potential ext.Vdd. Array operating potential Vdds is determined from the reliability of an insulating film which constitutes a memory cell capacitor. The recent reduction in the design rule leads to reduction in the thickness of the insulating film. Then, decrease of a potential difference applied to the film is required. Accordingly, there arises a need for decrease of array operating potential Vdds because of the reduced thickness of the insulating film.
However, in terms of an array operating margin, the lowered level of array operating potential Vdds is disadvantageous.
FIG. 7 is a circuit diagram showing a partial structure of a memory cell array in a DRAM.
Referring to FIG. 7, the memory cell array in the DRAM includes a sense amplifier 30, a bit line equalize circuit 20, and a memory cell 10.
Sense amplifier 30 includes P channel MOS transistors P1 and P2 and N channel MOS transistors N1 and N2.
P channel MOS transistor P1 is connected between a node A3 and a P channel MOS transistor P3, and P channel MOS transistor P2 is connected between a node A4 and P channel MOS transistor P3.
N channel MOS transistor N1 is connected between node A3 and an N channel MOS transistor N3, and N channel MOS transistor N2 is connected between node A4 and N channel MOS transistor N3.
P channel MOS transistor P1 and N channel MOS transistor N1 have respective gates connected to node A4 and P channel MOS transistor P2 and N channel MOS transistor N2 have respective gates connected to node A3. Node A3 is connected to a bit line BL and node A4 is connected to a bit line ZBL.
The source of P channel MOS transistor P3 is connected to an internal supply voltage generating circuit (VDC) 40 via a sense power supply line VSH (interconnect resistance R1) and the gate thereof is connected to a node ZSOP.
N channel MOS transistor N3 is grounded via a node VSL (interconnect resistance R2).
Bit line equalize circuit 20 includes an N channel MOS transistor N4 connected between bit lines BL and ZBL and N channel MOS transistors N5 and N6 connected in series between bit lines BL and ZBL. Respective gates of N channel MOS transistors N4 to N6 are connected to a node A2. The connecting point of N channel MOS transistors N5 and N6 is connected to a node A1. Node A2 receives a bit line equalize signal BLEQ and node A1 receives a bit line potential Vbl. Bit line equalize circuit 20 equalizes the potentials on bit lines BL and ZBL to bit line potential Vbl in response to rising of bit line equalize signal BLEQ to H level of an activation level. Bit line potential Vbl is equal to half of array operating potential, Vdds/2.
Memory cell 10 includes an N channel MOS transistor N7 for access and a capacitor C1 for information storage. The gate of N channel MOS transistor N7 in memory cell 10 is connected to a word line WL of a corresponding row. N channel MOS transistor N7 is connected between bit line BL and one electrode (storage node SN) of capacitor C1. The other electrode of capacitor C1 receives a cell plate potential Vcp. Word line WL activates memory cell 10. Paired bit lines BL and ZBL supply/receive a data signal to and from a selected memory cell.
When memory cell 10 holds H data, a data reading operation is performed as described below.
FIG. 8 is a timing chart showing an operation of sense amplifier 30 in FIG. 7.
Referring to FIG. 8, in a precharge state prior to time T1, bit line equalize signal BLEQ in bit line equalize circuit 20 has H level and accordingly N channel MOS transistors N4 to N6 in bit line equalize circuit 20 are turned on. Then, before time T1, respective potentials on paired bit lines BL and ZBL are precharged to bit line potential Vbl which is the intermediate potential between array operating potential Vdds of an H data potential and ground potential GND of an L data potential.
At time T1, word line WL is activated to H level so that N channel MOS transistor N7 in memory cell 10 is turned on and the H data held in memory cell 10 is transmitted to bit line BL. Consequently, the potential on bit line BL increases from bit line potential Vbl by a minute potential dV. The potential on bit line ZBL stays at bit line potential Vbl and thus a potential difference occurs between paired bit lines BL and ZBL.
At time T2, sense amplifier activation signals ZS0P and S0N become respectively to L and H levels so that P channel MOS transistor P3 and N channel MOS transistor N3 are turned on and sense amplifier 30 is activated. Then, the potential difference between paired bit lines BL and ZBL is amplified and bit line BL and storage node SN of memory cell 10 are raised to array operating potential Vdds which is the potential of H data. Moreover, the potential on bit line ZBL is lowered from bit line potential Vbl to ground potential GND.
It is supposed here that P channel MOS transistors P1 and P2 constituting sense amplifier 30 both have a threshold potential Vthp and N channel MOS transistors N1 and N2 constituting sense amplifier 30 both have a threshold potential Vthn. In order for sense amplifier 30 to start its operation at time T2, it is necessary that gate-source potential Vgs of P channel MOS transistors P1 and P2 should be higher than potential Vthp and gate-source potential Vgs of N channel MOS transistors N1 and N2 should be higher than potential Vthp. Gate-source potential Vgs can be represented by the following equation when minute potential dV is ignored.
Vgs=Vbl=Vdds/2
Then, for operation of sense amplifier 30, array operating potential Vdds should have the relation below.
Vdds greater than max(2xc3x97Vthn, 2xc3x97|Vthp|)xe2x80x83xe2x80x83(1)
Accordingly, array operating potential Vdds on sense power supply line VSH should be any potential which satisfies relation (1).
Further, an initial operating speed of sense amplifier 30 is determined by respective differences, Vgsxe2x88x92|Vthp| and Vgsxe2x88x92Vthn, between gate-source potential Vgs of respective MOS transistors in sense amplifier 30 and threshold voltages Vthp and Vthn of respective MOS transistors.
In view of this, if threshold voltages Vthp and Vthn of respective transistors vary due to change in a manufacturing process, a decreased array operating potential Vdds results in an insufficient operation margin of sense amplifier 30. In addition, if the decreased array operating potential Vdds makes it impossible to obtain an enough Vgsxe2x88x92|Vthp| or Vgsxe2x88x92Vthn, sense amplifier 30 requires an extended operating time.
After time T2 in FIG. 8, the potentials on sense power supply line VSH and node VSL during operation of sense amplifier 30 change transitionally depending on the interconnect resistances of sense power supply line VSH and node VSL, response rate of VDC circuit 40 and the like. In other words, the potential on sense power supply line VSH decreases to the lowest level at time T3 and the potential on node VSL increases to the highest level at time T3. Such a variation of the potentials on sense power supply line VSH and node VSL during the sensing operation considerably deteriorates the operating speed of sense amplifier 30.
In order to resolve the problem of insufficient operation margin of sense amplifier 30 due to the reduction of array operating potential Vdds, xe2x80x9coverdrive methodxe2x80x9d is proposed as a method of supplying charges to sense power supply line VSH.
One example of the overdrive method is described below that is proposed in Japanese Patent Laying-Open No. 11-250665 and Takasi Kono, 1999 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 123-124.
FIG. 9 is a circuit diagram showing a partial structure of a memory cell array in a DRAM including a sense amplifier drive circuit according to the overdrive method.
Referring to FIG. 9, a sense amplifier operating voltage generating circuit 90 is provided instead of VDC circuit 40 in the circuit diagram of FIG. 7.
FIG. 10 is a circuit diagram of sense amplifier operating voltage generating circuit 90 in FIG. 9.
Referring to FIG. 10, sense amplifier operating voltage generating circuit 90 includes a reference potential generating circuit 100, a selector circuit 150, a shifter circuit 160, a VDC circuit 170, a P channel driver circuit 200 and a decoupling capacitor C2.
Reference potential generating circuit 100 includes a low-pass filter (LPF) 110 for eliminating noise on an external supply potential ext.Vdd, a constant current circuit 120, and an output circuit 130 for outputting a predetermined voltage. Output circuit 130 includes a first reference potential output stage 131 and a second reference potential output stage 136.
Low-pass filter 110 includes a resistor R20 and a capacitor C20 connected in series between an external supply node ext.Vdd and a ground node GND, and outputs to constant current circuit 120 a potential with noise on external supply potential ext.Vdd removed therefrom.
Constant current circuit 120 includes a P channel MOS transistor P10 having its source connected to a node A5 and its gate and drain connected to a node A6, an N channel MOS transistor N10 connected between node A6 and ground node GND and having its gate connected to a node A7, a resistor R21 connected between node A5 and the source of a P channel MOS transistor P11, P channel MOS transistor P11 connected between resistor R21 and node A7 and having its gate connected to node A6, and an N channel MOS transistor N11 having its source connected to ground node GND and drain and gate connected to node A7.
Constant current circuit 120 generates a constant current Ir which does not depend on external supply potential ext.Vdd.
The first reference potential output stage 131 in output circuit 130 is constituted of P channel MOS transistors P12 to P15. P channel MOS transistor P12 simply supplies constant current Ir while P channel MOS transistors P13 to P15 operate as resistors. Then, the first reference potential output stage 131 outputs a potential Vrefs equal to an array operating potential Vdds. The second reference potential output stage 136 constituted of P channel MOS transistors P16 to P19 outputs a potential Vrefp equal to an internal potential Vddp used by peripheral circuitry of the memory cell array portion.
Selector circuit 150 includes a transfer gate 151 connected to the second reference potential output stage 136, a transfer gate 152 connected to the first reference potential output stage 131, and an inverter 153. Transfer gates 151 and 152 have respective gates receiving a signal PRE for inactivating a row-related circuit to output potential Vrefp when signal PRE has H level and output potential Vrefs when signal PRE has L level.
Shifter circuit 160 includes an N channel MOS transistor N20 connected between nodes A10 and A12 and having its gate receiving an output signal from selector circuit 150, an N channel MOS transistor N22 connected between node A10 and ground node GND and having its gate connected to a node A11, an N channel MOS transistor N21 connected between nodes A12 and A11 and having its gate receiving a potential on a sense power supply line VSH, and an N channel MOS transistor N23 having its gate and drain connected to node A11 and its source connected to ground node GND. A signal REF is output from node A10 of shifter circuit 160 while a signal SIG is output from node A11.
VDC circuit 170 includes a comparator 180 constituted of a differential amplifier circuit and a P channel driver circuit 190 including a P channel MOS transistor P22 connected to sense power supply line VSH and external supply node ext.Vdd.
Comparator 180 includes a P channel MOS transistor P20 having its source connected to a node A13 supplied with external supply potential ext.Vdd and having its gate and drain connected to a node A14, an N channel MOS transistor N24 connected between nodes A14 and A16 and having its gate receiving signal SIG, a P channel MOS transistor P21 connected between nodes A13 and A15 and having its gate connected to node A14, an N channel MOS transistor N25 connected between nodes A15 and A16 and having its gate receiving signal REF, and an N channel MOS transistor N26 connected between node A16 and ground node GND and having its gate receiving external supply potential ext.Vdd.
P channel MOS transistor P22 in P channel driver circuit 190 receives, at its gate, an output potential from comparator 180 and supplies the potential to sense power supply line VSH.
Signals SIG and REF supplied from shifter circuit 160 change in respective ranges centering on respective levels which are respectively almost a half of the potential from selector circuit 150 and almost a half of the potential on sense power supply line VSH. Then, N channel MOS transistors N24 and N25 in comparator 180 receiving these signals can operate in a saturation region even if the potential on node A16 is close to the ground potential. As a result, gate-source potential Vgs of P channel MOS transistor P22 in P channel driver circuit 190 can be increased. In other words, even if the transistor size of P channel MOS transistor P22 is relatively small, the VDC circuit having a satisfactory current supply capability can be implemented.
P channel driver circuit 200 includes a P channel MOS transistor P23 connected between an internal potential node Vddp and sense power supply line VSH and an inverter 202 connected to the gate of P channel MOS transistor P23.
P channel MOS transistor P23 in P channel driver circuit 200 is turned on when signal PRE has H level to supply internal potential Vddp to sense power supply line VSH.
Sense amplifier operating voltage generating circuit 90 having the above circuit structure according to the overdrive method operates as discussed below.
FIG. 11 is a timing chart showing an operation of sense amplifier operating voltage generating circuit 90 shown in FIG. 10.
Referring to FIG. 11, in a precharge state prior to time T4, signal PRE has H level so that an output signal supplied from selector circuit 150 is potential Vrefp. Then, internal potential Vddp equal to potential Vrefp is supplied from VDC circuit 170 to sense power supply line VSH at the time of precharge. At the same time, P channel MOS transistor P23 in P channel driver circuit 200 is turned on so that internal potential Vddp is supplied from P channel driver circuit 200 to sense power supply line VSH.
Accordingly, when signal PRE has H level before time T4, sense power supply line VSH and decoupling capacitor C2 are always supplied with internal potential Vddp at the time of precharge.
Prior to time T4 when word line WL is activated, signal PRE becomes L level. Then, P channel MOS transistor P23 in P channel driver 200 is turned off and accordingly sense power supply line VSH and decoupling capacitor C2 are separated from internal potential Vddp. The potential output from selector circuit 150 is potential Vrefs so that the potential supplied from VDC circuit 170 to sense power supply line VSH is array operating potential Vdds.
At time T5, activation signals S0N and ZS0P become H and L levels respectively to start the operation of sense amplifier 30. Then, charges accumulated on decoupling capacitor C2 flow onto sense power supply line VSH. As a result, the potential on sense power supply line VSH decreases lower than array operating potential Vdds to a decreased extent and accordingly a higher rate of the sense amplify operation is achieved.
The capacitance of decoupling capacitor C2 can appropriately be set to make the potential on sense power supply line VSH after completion of sensing operation equal to array operating potential Vdds which is H data potential. However, the potential supplied from VDC circuit 170 to sense power supply line VSH at time T4 is array operating potential Vdds, therefore, even if sense power supply line VSH has its potential equal to or lower than array operating potential Vdds due to insufficient charges accumulated on the decoupling capacitor in the sensing operation, VDC circuit 170 supplies charges corresponding to the shortage of charges. In this way, the potential on sense power supply line VSH is kept at array operating potential Vdds.
Sense amplifier operating voltage generating circuit 90 having the circuit structure shown in FIG. 10 can be used to increase the rate of sensing operation in the initial stage relative to the conventional sense amplifier and thus a sufficient sense margin can be secured even at a low array operating potential Vdds.
The reason for the above advantage is that, in the initial stage of sensing operation by sense amplifier operating voltage generating circuit 90, gate-source potential Vgs of each MOS transistor in sense amplifier 30 increases from the conventional (Vdds/2) to (Vddpxe2x88x92Vdds/2) by (Vddpxe2x88x92Vdds).
The sensing operation by sense amplifier operating voltage generating circuit 90 having the circuit structure shown in FIG. 10 is effective when external supply potential ext.Vdd, internal potential Vddp and array operating potential Vdds have the following relation:
external supply potential ext.Vdd greater than internal potential Vddp greater than array operating potential Vdds.
Another example of the overdrive method is disclosed as an overdrive sensing method in Japanese Patent Laying-Open No. 11-250665 described below.
FIG. 12 is a circuit diagram of a sense amplifier drive circuit according to the second overdrive method.
Referring to FIG. 12, a sense amplifier operating voltage generating circuit 300 includes a reference potential generating circuit 301 outputting a potential Vrefs equal to an array operating potential Vdds, a VDC circuit 306, a P channel driver circuit 307 and a decoupling capacitor C3.
Reference potential generating circuit 301 generates reference potential Vrefs equal to array operating potential Vdds and supplies reference potential Vrefs to VDC circuit 306.
VDC circuit 306 includes a comparator 302 and a P channel driver circuit 303. Comparator 302 is a differential amplifier circuit constituted of P channel MOS transistors P20 and P21 and N channel MOS transistors N24, N25 and N26. The gate of N channel MOS transistor N24 receives the potential on a sense power supply line VSH while the gate of N channel MOS transistor N25 receives reference potential Vrefs. P channel driver circuit 303 includes a P channel MOS transistor P22 connected between an external supply potential ext.Vdd and sense power supply line VSH.
P channel driver circuit 307 includes a P channel MOS transistor P30 which is connected between external supply node ext.Vdd and sense power supply line VSH and has its gate supplied with a signal xcfx86.
Sense amplifier operating voltage generating circuit 300 having the above circuit structure operates as described below.
FIG. 13 is a timing chart showing an operation of sense amplifier operating voltage generating circuit 90 shown in FIG. 12.
Referring to FIG. 13, prior to time T6, signal xcfx86 is at L level so that P channel MOS transistor P30 is turned on and sense power supply line VSH is precharged to external supply potential ext.Vdd.
At time T6, sense amplifier activation signals S0N and ZS0P become respectively to H and L levels to start the operation of sense amplifier 30. Then, each MOS transistor in sense amplifier 30 has its gate-source potential Vgs higher than the conventional one. Signal xcfx86 stays at L level until time T7 and sense power supply line VSH is provided with external supply potential ext.Vdd and accordingly the sense amplifier operation is increased in rate. On the other hand, if there is a shortage of charges required for sensing operation after time T7, charges are supplied from VDC circuit 306 and accordingly the potential on sense power supply line VSH is maintained at array operating potential Vdds.
When sense amplifier operating voltage generating circuit 90 or 300 according to the overdrive method as described above is employed to perform a sensing operation, the potential on sense power supply line VSH in sensing operation never exhibits such a remarkable decrease as that occurs at time T3 in FIG. 8. Consequently, the rate of sensing operation can be increased.
However, a problem arises when, in a semiconductor integrated circuit including the sense amplifier operating voltage generating circuit of the overdrive method, external supply potential ext.Vdd is decreased for the purpose of saving power.
It is supposed here that external supply potential ext.Vdd to be provided to a semiconductor integrated circuit device including a sense amplifier operating voltage generating circuit of the overdrive method is reduced for saving power, and consequently the relation, external supply potential ext.Vdd=internal potential Vddp is established.
In this case, in sense amplifier operating voltage generating circuits 90 and 300 of the overdrive method, respective decoupling capacitors C2 and C3 being precharged are both supplied with external supply potential ext.Vdd. Here, external supply potential ext.Vdd varies in an allowable range defined by a specification. Then, the amount of charges accumulated on decoupling capacitors C2 and C3 being precharged varies.
If the amount of accumulated charges is smaller than that necessary for a sensing operation, an amount of charges corresponding to the shortage is provided from VDC circuits 170 and 306 and thus no problem occurs. However, if the variation of external supply potential ext.Vdd causes the amount of accumulated charges to be larger than a necessary amount of charges, the potential on sense power supply line VSH in sensing operation becomes higher than H data potential which is not preferable in terms of reliability of memory cells.
Specifically, suppose that capacitance of decoupling capacitors C2 and C3 is Cd, total amount of negative charges on bit line BL or ZBL is Cba, precharge potential on sense power supply line VSH is Vpre and precharge level of a bit line is Vbl (=Vdds/2), and the following relation is satisfied.
Cdxc3x97(Vprexe2x88x92Vdds)=Cbaxc3x97Vblxe2x80x83xe2x80x83(2)
In this case, if external supply potential ext.Vdd is higher than precharge potential Vpre, the potential on sense power supply line VSH in sensing operation is higher than H data potential which is not preferable in terms of reliability.
One object of the present invention is to provide a semiconductor integrated circuit device achieving power savings without decrease in the operating rate of a sense amplifier and without supply of charges more than necessary to a memory cell.
A semiconductor integrated circuit device according to the present invention includes paired bit lines, a memory cell connected to one of the paired bit lines, a sense amplifier for amplifying a potential difference between the paired bit lines generated by reading of data from the memory cell, and a sense amplifier operating voltage generating circuit for supplying a voltage accumulated in the memory cell to the sense amplifier in an active period of the sense amplifier. The sense amplifier operating voltage generating circuit includes an internal potential supply node connected to the sense amplifier, a first voltage supply circuit for outputting, when an external supply voltage is higher than a predetermined voltage, the predetermined voltage as an output voltage to the internal potential supply node and outputting, when the external supply voltage is lower than the predetermined voltage, a voltage equal to the external supply voltage as an output voltage to the internal potential supply node, and a decoupling capacitor connected to the internal potential supply node.
Preferably, the first voltage supply circuit is stopped from operating in the active period of the sense amplifier.
Still preferably, the first voltage supply circuit includes a reference voltage generating circuit for outputting a voltage lower than the external supply voltage as a reference voltage, a shift circuit for reducing the output voltage to output the reduced voltage, and a voltage downconverter circuit receiving the reference voltage and the reduced voltage to output the output voltage.
Still more preferably, the voltage downconverter circuit includes a comparator circuit receiving the reference voltage and the reduced voltage to output a result of comparison between the reference voltage and the reduced voltage, and a switching element connected to an external supply node receiving the external supply voltage and the internal potential supply node, and the switching element receives the result of comparison from the comparator circuit to control the output voltage of the internal potential supply node.
Accordingly, it is possible to avoid charges more than necessary from being supplied to bit lines in a sense amplifier operation.
Still more preferably, the shift circuit includes a plurality of resistor elements connected in series between the internal potential supply node and a ground node.
The output voltage can thus be reduced.
Still more preferably, the shift circuit includes a first transistor and a second transistor connected in series between the external supply node and the ground node, and the output voltage is input to a control electrode of the first transistor and the reference voltage is input to a control electrode of the second transistor.
Then, variations of the output voltage can readily be adjusted due to changes of manufacture process of the semiconductor integrated circuit device.
Still more preferably, the sense amplifier operating voltage generating circuit further includes a second voltage supply circuit for outputting the predetermined voltage to the internal potential supply node when the output voltage held in the decoupling capacitor by charging is lower than the predetermined voltage in an inactive period of the sense amplifier.
Still more preferably, the second voltage supply circuit supplies the predetermined voltage in the active period of the sense amplifier.
Accordingly, a shortage of charges can be prevented that are to be supplied to bit lines in a sense amplifier operation.
Still more preferably, the predetermined voltage is a lower limit of the external supply voltage determined by a specification.
Then, excessive supply of charges to bit lines due to variations of the external supply voltage can be prevented.
According to the present invention, the semiconductor integrated circuit device can be provided that achieves power savings without decrease in the operating rate of the sense amplifier.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.